LATENCY=5CLK
HPB Memory Timing Register.
| LATENCY | RAM Latency Clock Cycles. 0 (5CLK): 5 clock cycles. 1 (6CLK): 6 clock cycles. 14 (3CLK): 3 clock cycles. 15 (4CLK): 4 clock cycles. |
| WCSH | Write chip select hold after CK falling edge. |
| RCSH | Read chip select hold after CK falling edge. |
| WCSS | Write chip select setup time to next CK rising edge. |
| RCSS | Read chip select setup time to next CK rising edge. |
| WCSHI | Write chip select high between operations. |
| RCSHI | Read chip select high between operations. |